Conventional nonvolatile PROM (Programmable Read-Only Memory) memories can be divided into two classes: EPROMs (Electrically Programmable Read-Only Memories) and EEPROMs (Electrically Erasable/Programmable Read-Only Memories). EPROMs use channel hot electron injection for byte-programming, and apply ultraviolet light exposure for erase operations. EEPROMs generally employ Fowler-Nordheim (F-N) tunneling for both programming and erasing. Due to the small cell size and simple cell design and fabrication process, EPROMs can be produced with higher density and lower cost compared to EEPROMs. On the other hand, EEPROMs offer the capability of byte-erase as well as the convenience of in-system electrical reusability. Recently, the flash memory has gained significant attention as it promises to combine the advantages of EPROM density with EEPROM electrical erasability.
At present time, there are several approaches to flash memory technology. The multifarious designs sort themselves into two basic approaches, distinguished by whether they require one or two voltage supplies. Both can trace their lineage to EPROM technology, using a floating gate structure but with a thinner gate oxide. However, they differ in their cell structure as to whether they require one or several transistors per cell. In general, the one-transistor cell requires a 12 volt supply for programming and a 5 volt supply for reading, but yields a small cell size. This results in higher density, smaller chip size, and lower cost than the 5 volt only approach.
The self-aligned stacked-gate cell based on ETOX (EPROM Tunnel-Oxide) technology, is the typical for the one transistor school. There are three keys to ETOX cell operation: (1) a very high-quality oxide, (2) unique drain and source structure, optimized for program and erase operations respectively, and (3) the use of complementary, adaptive program and erase algorithms. This combination supports well-controlled erasure and reprogramming of the simple stacked-gate ETOX cell. One problem with the single-transistor cell, however, is the possibility of over-erasure and consequent current leakage, resulting in false data readings. This occurs when a cell in the zero state receives an erase pulse, whereby it can be driven into depletion mode. The column-sense amplifier can read this leakage current falsely as an erased cell.
The use of a truncated floating gate, or stepped-gate cell, also provides a flash EEPROM capability. The truncated floating gate's voltage must be accompanied by a select-gate voltage for turning on the cell. The programming operation and reading function are identical to those used in EPROM and ETOX flash cells. The stepped-gate structure's primary drawback is an electrical-stress-induced charge loss during programming known as "program disturb", whereby floating-gate charge is lost through the drain region of the cell. This and various other stresses are present with all floating-gate technologies and must be designed and processed out. Very tight stepped-gate process control can provide a sufficient "operating window", but in any case, electrical stresses are significant factors in cycle-related programming failures. Furthermore, the problem is exacerbated by slower programming, caused by a longer cell channels.
Another approach that automatically protects against over-erasure is to let the floating gate control only half of the channel and let the other half of the channel be controlled by the control gate. In this manner, the transistor would be off even if the floating gate is positively charged. Such a cell is known as a split-gate cell. However, the longer channel length results in somewhat longer programming times and/or higher bit-line voltage during programming and may increase the cell size.
The dual-power-supply requirements of most of conventional flash EEPROMs add cost and space penalties for system design, and for this reason, many innovative single-supply flash memory technologies have been developed. The advantage of these approaches in memory applications is that they can provide a significant cell area reduction without further stretching the device limits. However, the complicated fabrication steps involved with these cell structures may result in a loss of cost competitiveness in the memory market.
In summary, there are many routes to the design, construction, and fabrication of flash memories, including those described above. All the technologies trace their lineage to EPROM technology, using a floating-gate structure but with a thinner gate oxide. Each variation has its advantages and disadvantages, resulting from the tradeoff between cost and system requirements. As the combination of high density, low cost, and electrical reprogrammability makes flash EPROM a candidate for data storage, the combination of high density, low power, flexibility of fast bulk-erase and byte-program and/or bulk-program and byte-erase makes flash memory a good candidate for programmable logic devices.
Hence, there was a need in the art for a nonvolatile flash memory structure affording high speed programming and erasing operations as well as fast reading speed with low voltages and low power consumption.